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<div class="title">OWIRE_TypeDef结构体 参考<div class="ingroups"><a class="el" href="group___c_m_s_i_s.html">CMSIS</a> &raquo; <a class="el" href="group__wb32l003.html">Wb32l003</a> &raquo; <a class="el" href="group___device___peripheral__peripherals.html">Device_Peripheral_peripherals</a></div></div>  </div>
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成员变量</h2></td></tr>
<tr class="memitem:a10e4b0d52a1683e587437b67bdf0efc5"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_o_w_i_r_e___type_def.html#a10e4b0d52a1683e587437b67bdf0efc5">CR</a></td></tr>
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<tr class="memitem:a266393514289acb6c3eab9ae14a5ea30"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_o_w_i_r_e___type_def.html#a266393514289acb6c3eab9ae14a5ea30">RDSMPCNT</a></td></tr>
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<tr class="memitem:a38392e124566b8272c3a5ea9b792b2d4"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_o_w_i_r_e___type_def.html#a38392e124566b8272c3a5ea9b792b2d4">CMD</a></td></tr>
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<h2 class="groupheader">结构体成员变量说明</h2>
<a id="a276ad33d6a963a7c77cdfaaaecd97687"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a276ad33d6a963a7c77cdfaaaecd97687">&#9670;&nbsp;</a></span>BITRATECNT</h2>

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<p>One-wire bit rate design count register, Address offset: 0x010 </p>

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<a id="a38392e124566b8272c3a5ea9b792b2d4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a38392e124566b8272c3a5ea9b792b2d4">&#9670;&nbsp;</a></span>CMD</h2>

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<p>One_wire bus operate command register, Address offset: 0x024 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a10e4b0d52a1683e587437b67bdf0efc5">&#9670;&nbsp;</a></span>CR</h2>

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<p>One-wire model control register, Address offset: 0x000 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ad6f66ed46796520a338eb3c3c198c8f1">&#9670;&nbsp;</a></span>DATA</h2>

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<p>One_wire data register, Address offset: 0x020 </p>

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<a id="a945b57f9f34b9a6e53841a840f4bcbd6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a945b57f9f34b9a6e53841a840f4bcbd6">&#9670;&nbsp;</a></span>DRVCNT</h2>

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<p>One-wire main read/write pull0 drive time register, Address offset: 0x014 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6257a1dba4f7f3f833c7fe9c66a5713f">&#9670;&nbsp;</a></span>INTCLR</h2>

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          <td class="memname">__IOM uint32_t INTCLR</td>
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<p>One-wire interrupt status clean register, Address offset: 0x030 </p>

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<a id="ae882b3f7e12b9f3b74cf834193554d32"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae882b3f7e12b9f3b74cf834193554d32">&#9670;&nbsp;</a></span>INTEN</h2>

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          <td class="memname">__IOM uint32_t INTEN</td>
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<p>One-wire interrupt enable register, Address offset: 0x028 </p>

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<a id="a4ab41082ab4032265c481db3bf7b9708"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a4ab41082ab4032265c481db3bf7b9708">&#9670;&nbsp;</a></span>NFCR</h2>

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          <td class="memname">__IOM uint32_t NFCR</td>
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<p>One-wire input endpoint control register, Address offset: 0x004 </p>

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<a id="abfcc6a2c4e291be5f75aee0cd82f593d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#abfcc6a2c4e291be5f75aee0cd82f593d">&#9670;&nbsp;</a></span>PRESCNT</h2>

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<p>One-wire device presence pulse count register, Address offset: 0x00C </p>

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<a id="a266393514289acb6c3eab9ae14a5ea30"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a266393514289acb6c3eab9ae14a5ea30">&#9670;&nbsp;</a></span>RDSMPCNT</h2>

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<p>One-wire main read sample time setting register, Address offset: 0x018 </p>

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<a id="aab513a8ffc1167cb75f4b44530b6d044"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aab513a8ffc1167cb75f4b44530b6d044">&#9670;&nbsp;</a></span>RECCNT</h2>

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          <td class="memname">__IOM uint32_t RECCNT</td>
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<p>One-wire recover time count register, Address offset: 0x01C </p>

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<a id="a9b63c695e506e2a112bb948cd950f878"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a9b63c695e506e2a112bb948cd950f878">&#9670;&nbsp;</a></span>RSTCNT</h2>

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          <td class="memname">__IOM uint32_t RSTCNT</td>
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<p>One-wire master reset pulse count register, Address offset: 0x008 </p>

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<a id="a95fcc7996cf77f1fe70b6ad5bae01549"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a95fcc7996cf77f1fe70b6ad5bae01549">&#9670;&nbsp;</a></span>SR</h2>

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<p>One-wire status register, Address offset: 0x02C </p>

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